Before I joined Intel, I've always had this idea in my mind - to have a highspeed FPGA as a coprocessor. I think this is a much better time to propose this solution to the world than it's ever been. With the buzz going around Larrabee and its need for a fixed function unit such as the rasterization unit for GPU, it would be so much more flexible if this is implemented as a block of FPGA. The driver is then responsible for converting this block into whatever the application sees fit. Anything that could not fit in that cGPU paradigm can be hardware accelerated via the FPGA block.
Any take on this, Intel?
2 comments:
The ASIP concept is great. (Application-Specific Instruction Processor)
"Project chimaera" is quite old and iirc it did not provide any C example, alas.
Apart from theoretical papers, where do we find any valuable example of C code mixed with the usage of an affordable FPGA configured as an ASIP ?
Let's say you use Linux. How does the FPGA "know" where to write inside the external RAM ?
Didn't actually notice this comment until now!
You wouldn't use Linux to "write inside the external RAM", or C for that matter. You'd be writing in VHDL or another similar language to talk to a (or the same CPU) memory controller which gives you the ability to access the RAM.
Anyway Intel will be shipping a Xeon with embedded FPGA soon enough. My idea was just 15 years too early for Intel.
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